This invention relates in general to the field of radio communications and more specifically to a frequency synthesizer.
A large reduction of the transistor features in recently developed deep-submicron complementary metal-oxide semiconductor (CMOS) processes shifts the design paradigm towards more digitally intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of the number of devices used, but rather in terms of the occupied silicon area used. A typical digital cellular telephone on the market today contains over a million transistors. Analog and radio frequency (RF) circuits, on the other hand, do not scale down very well. A low-noise charge pump, or a low-distortion image-rejection modulator, both good examples of classical RF transceiver components, occupy roughly about the same amount of semiconductor surface area as is used for tens of thousands of digital gates. This is equivalent to a lot of digital signal processing (DSP) power. Consequently, there are numerous incentives to look for digital solutions for both analog and RF circuits. Unfortunately, very little research work on this topic has been disclosed so far.
There are a few frequency synthesis techniques found in RF communication products, they include direct-digital, indirect or phase-locked loop (PLL), and hybrids that are a combination of the direct and indirect approaches. Each of these methods of frequency synthesis has advantages and disadvantages; hence each application requires selection based upon the most acceptable combination of compromises to the designer.
Indirect synthesis, also called phase-locked loop (PLL), compares the output of a voltage-controlled oscillator (VCO) with a phase of a reference signal, fREF, as shown in the prior art PLL of FIG. 1. As the output of the PLL drifts, detected errors produce correction commands to the VCO, which responds accordingly. Error detection occurs in the phase frequency detector (PFD), which adds phase noise close to the carrier, though a PLL can outperform direct synthesis techniques at larger offsets. Fine frequency steps degrade phase noise, and fast switching is difficult to achieve with a PLL design even with the use of aggressive VCO pre-tuning techniques.
In general, an indirect synthesizer uses a PLL loop and a programmable fractional-N divider that multiplies the stable frequency, fREF. In the loop, a loop filter (LF) is present so as to suppress spurs produced in the PFD so that they do not cause unacceptable frequency modulation in the VCO. However, the LF causes the degradation in transients, which limits the switching time. Therefore, the requirements for both the frequency switching time and the suppression of spurs are in conflict. Classical PLL-based frequency synthesizers are only suitable for narrow-band frequency modulation schemes, in which the modulating data rate is well within the PLL loop bandwidth.
The second major synthesis technique currently used today is direct-digital frequency synthesis (DDFS) which uses logic and memory components to digitally construct the desired output signal, and a data conversion device to convert it from the digital to the analog domain, as shown in FIG. 2. The DDFS method of constructing a signal is almost all digital, and the precise amplitude, frequency, and phase are known and controlled at all times. For these reasons, the switching speed is considered extremely high, but the power consumption could be excessive at high clock frequencies. The DDFS method is not entirely digital in the true sense of the word since it requires a digital-to-analog converter (DAC) and a low-pass filter to attenuate the spurious frequencies caused by the digital switching. In addition, a very stable clock of at least three times the output frequency is required, and the total power consumption is not acceptable for designs used in mobile communications.
Because it is very costly to implement a DDFS at frequencies of interest for wireless communications (e.g., multi-GHz range), this technique is currently being used mainly for military applications. Due to its waveform reconstruction nature, the DDFS technique is best suited for implementing wideband transmit modulation, as well as fast channel-hopping schemes. In FIG. 3, there is shown the prior art front-end of the phase accumulator shown in FIG. 2. The front-end uses an arithmetic adder that combines the frequency control word (FCW) components of the selected channel and the frequency-modulating data.
In certain design applications, it is necessary to combine the two (direct and indirect) major synthesis techniques such that the best features from each method are emphasized. For example, the wideband modulation and fast channel-hopping capability of the DDFS method, is combined with a frequency multiplication property of a PLL loop that up-converts it to the RF band. This is shown in FIG. 4 as a hybrid synthesizer 400 including a DDFS 402 and a PLL 404. The DDFS 402 generates a stable frequency reference to the main PLL loop 404. Since the DDFS 402 operates at a low frequency, its major limitation of high power is not a concern.
Deep-submicron CMOS processes present new integration opportunities to the designer, but make it difficult to implement traditional analog circuits. For example, frequency control input of a low-voltage deep-submicron CMOS oscillator is an extremely challenging task due to its highly nonlinear frequency versus voltage characteristics and low voltage headroom making it susceptible to the power supply and substrate noise. In such a low supply voltage case, the dynamic range of the signal and thus the signal-to-noise (S/N) ratio will degrade significantly. In this case, a circuit designer has to look for alternative solutions, such as utilizing a voltage doubler. Furthermore, the advanced CMOS processes typically use low resistance P-substrate that is an effective means in combating latch-up problems, but exacerbates substrate noise coupling into the analog circuits. This problem only gets worse with scaling down of the supply voltage. In order to address the various deep-submicron RF integration issues, some new and radical system and architectural changes have to be discovered.